Linus Torvalds writes: (Summary) wrote:
Uhhuh.
The page directories should *definitely* always be in cacheable memory, so it should be ok for that bit to be 0, and it's possible that setting it to 1 will seriously screw up performance. But the fact that that fixes it for you does indicate that it's not just a stale TLB entry or something, it really is some CPU using page tables after they have been free'd and been re-allocated to something else (and *then* they may point to garbage).
else (and *then* they may point to garbage).
So I do think it's a sign that we definitely need that IPI for you.
[...]
ormance optimization that[...]
assumes PML4, PDP, PDE, and PTE entries are in cacheable WB-DRAM Uhhuh.Uhhuh.
The page directories should *definitely* always be in cacheable memory, so it should be ok for that bit to be 0, and it's possible that setting it to 1 will seriously screw up performance. But the fact that that fixes it for you does indicate that it's not just a stale TLB entry or something, it really is some CPU using page tables after they have been free'd and been re-allocated to something else (and *then* they may point to garbage).
else (and *then* they may point to garbage).
So I do think it's a sign that we definitely need that IPI for you.